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71M6545/71M6545H Data Sheet
RESET has been high at least for 2 μs. Note that TMUX and the RTC are not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit ( I/O RAM 0x 2200[3] ) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes
the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
71M6545/H. It does not trigger the reset sequence. This type of reset is intended to reset the MPU
program, but not to make other changes to the chip’s state.
3.4
Data Flow and Host Communication
The data flow between the Compute Engine (CE) and the host is shown in Figure 22 . In a typical
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IADC0-
IADC1, VADC8 (VA), IADC2-IADC3, etc., performing calculations to measure active power (Wh),
reactive power (VARh), A 2 h, and V 2 h for four-quadrant metering. These measurements are then
accessed by the host via the SPI interface, processed further and stored and/or displayed. For example,
to obtain the RMS current value in phase A, the host reads the I0SQSUM_X register of the CE, scales it
with VMAX, IMAX, and the LSB, as given in the CE Interface description (see 5.4 CE Interface
Description on page 100 ), and then performs a square-root operation. Similarly, momentary real power
and reactive power available via the WSUM_X and VARSUM_X registers only have to be scaled by the
host, while the apparent power has to be post-processed as follows:
S = P 2 + Q 2
Figure 22 illustrates the CE-to-host data flow.
71M6545/H
Pulses
TMUX
XFER_BUSY
XPULSE
YPULSE
VPULSE
WPULSE
CE_BUSY
Sag Warning
Data Ready
Interrupt
DIO1/interrupt
DIO2/interrupt
Host
Samples
MPU
MUX
CE
XRAM
Control
SPI
I/O RAM (Configuration RAM)
10/7/2010
Figure 22: Data Flow
In addition to the four pulse interrupts XPULSE, YPULSE, VPULSE, and WPULSE, the CE outputs two
interrupt signals: CE_BUSY and XFER_BUSY. XFER_BUSY signals the end of an accumulation interval
v2
69
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